This application note gives an overview of the Low Energy Timer (LETIMER) and demonstrates how to use its features to generate pulses, PWM and other waveforms while remaining in EM2 to achieve high energy efficiency.
1 Introduction
The unique LETIMERTM, the Low Energy Timer, is a 16-bit timer that is available in energy mode EM2 in addition to EM1 and EM0. Because of this, it can be used for timing and output generation when most of the device is powered down, allowing simple tasks to be performed while the power consumption of the system is kept at an absolute minimum. The LETIMER runs from the LFACLK which can be clocked by the LFXO, LFRCO or HFCORECLKLE/2. If clocked by the HFCORECLKLE/2 the LETIMER and other peripherals running from the LFACLK will not be available in EM2.
The LETIMER can be used to output a variety of waveforms with minimal software intervention.The waveforms include PWM, pulses with the duraction of one LFACLKLETIMER period and variable frequency waveforms. The LETIMER is also connected to the Real Time Counter (RTC), and can be configured to start counting on compare matches from the RTC.
An overview of the LETIMER module is shown in Figure 1.1 (p. 2) . The LETIMER is a
16-bit down-counter with two compare registers, LETIMERn_COMP0 and LETIMERn_COMP1. The LETIMERn_COMP0 register can optionally act as a top value for the counter. The repeat counter LETIMERn_REP0 allows the timer to count a specified number of times before it stops. Both the LETIMERn_COMP0 and LETIMERn_REP0 registers can be double buffered by the LETIMERn_COMP1 and LETIMERn_REP1 registers to allow continuous operation. The timer can generate a single pin output, or two linked outputs.
Figure 1.1. LETIMER Overview
2 LETIMER Features
2.1 Compare Registers
The LETIMER has two compare match registers, LETIMERn_COMP0 and LETIMERn_COMP1. Each of these compare registers are capable of generating an interrupt when the counter value LETIMERn_CNT becomes equal to their value. When LETIMERn_CNT becomes equal to the value of LETIMERn_COMP0, the interrupt flag COMP0 in LETIMERn_IF is set, and when LETIMERn_CNT becomes equal to the value of LETIMERn_COMP1, the interrupt flag COMP1 in LETIMERn_IF is set.
The compare values can be set using the LETIMER_CompareSet(LETIMER_TypeDef *letimer, unsigned int comp, uint32_t value) from the emlib.
2.2 Top Value
If COMP0TOP in LETIMERn_CTRL is set, the value of LETIMERn_COMP0 acts as the top value of the timer, and LETIMERn_COMP0 is loaded into LETIMERn_CNT on timer underflow. Otherwise the timer wraps around to 0xFFFF. The underflow interrupt flag UF in LETIMERn_IF is set when the timer reaches zero.
If BUFTOP in LETIMERn_CTRL is set, the value of LETIMERn_COMP0 is buffered by LETIMERn_COMP1. In this mode, the value of LETIMERn_COMP1 is loaded into LETIMERn_COMP0 every time LETIMERn_REP0 is about to decrement to 0.
2.3 Repeat Modes
By default, the timer wraps around to the top value or 0xFFFF on each underflow, and continues counting. The repeat counters can be used to get more control of the operation of the timer, including defining the number of times the counter should wrap around. There are four repeat modes available which are detailed in Table 2.1 (p. 3) .
Table 2.1. LETIMER Repeat Modes
| REPMODE | Mode | Description |
| 00 | Free | The timer runs until it is stopped |
| 01 | One-shot | The timer runs as long as LETIMERn_REP0 != 0. LETIMERn_REP0 is decremented at each timer underflow. |
| 10 | Buffered | The timer runs as long as LETIMERn_REP0 != 0. LETIMERn_REP0 is decremented on each timer underflow. If LETIMERn_REP1 has been written, it is loaded into LETIMERn_REP0 when LETIMERn_REP0 is about to be decremented to 0. |
| 11 | Double | The timer runs as long as LETIMERn_REP0 != 0 or LETIMERn_REP1 != 0. Both LETIMERn_REP0 and LETIMERn_REP1 are decremented at each timer underflow. |
The interrupt flags REP0 and REP1 in LETIMERn_IF are set whenever LETIMERn_REP0 or LETIMERn_REP1 are decremented to 0 respectively. REP0 is also set when the value of LETIMERn_REP1 is loaded into LETIMERn_REP0 in buffered mode.
The function LETIMER_RepeatSet(LETIMER_TypeDef *letimer, unsigned int rep, uint32_t value) from the emlib can be used to set the values of the repeat registers.
1.1.1 Free Mode
In the free running mode, the LETIMER acts as a regular timer, and the repeat counter is disabled. The LETIMER can be started by writing the START bit in LETIMERn_CMD and runs until it is stopped using the STOP bit in the same register.
1.1.2 One-shot Mode
The one-shot repeat mode is the most basic repeat mode. In this mode, the repeat register LETIMERn_REP0 is decremented every time the timer underflows, and the timer stops when LETIMERn_REP0 goes from 1 to 0. In this mode, the timer counts down LETIMERn_REP0 times, i.e. the timer underflows LETIMERn_REP0 times. LETIMERn_REP0 can be written while the timer is running to allow the timer to run for longer periods at a time without stopping.
1.1.3 Buffered Mode
The Buffered repeat mode allows buffered timer operation. When started, the timer runs LETIMERn_REP0 number of times. If LETIMERn_REP1 has been written since the last time it was used and it is nonzero, LETIMERn_REP1 is then loaded into LETIMERn_REP0, and counting continues the new number of times. The timer keeps going as long as LETIMERn_REP1 is updated with a nonzero value before LETIMERn_REP0 is finished counting down. If the timer is started when both LETIMERn_CNT and LETIMERn_REP0 are zero but LETIMERn_REP1 is non-zero, LETIMERn_REP1 is loaded into LETIMERn_REP0, and the counter counts the loaded number of times.
1.1.4 Double Mode
The Double repeat mode works much like the one-shot repeat mode with the difference that the LETIMER counts as long as either LETIMERn_REP0 or LETIMERn_REP1 is larger than 0.
1.2 Clock Source
The LETIMER clock source and its prescaler value are defined in the Clock Management Unit (CMU). The LFACLKLETIMERn has a frequency given by Equation 2.1 (p. 4) where the exponent LETIMERn is a 4 bit value in the CMU_LFAPRESC0 register.
| LETIMER Clock Frequency fLFACKL_LETIMERn = 32.768/2LETIMERn | (2.1) |
To use this module, the LE interface clock must be enabled in CMU_HFCORECLKEN0, in addition to the module clock. Clock enabling and prescaling is covered in AN0004 Clock Management Unit.
1.3 RTC Trigger
The LETIMER can be configured to start on compare match events from the Real Time Counter (RTC). If RTCC0TEN in LETIMERn_CTRL is set, the LETIMER will start on a compare match on RTC compare channel 0. In the same way, RTCC1TEN in LETIMERn_CTRL enables the LETIMER to start on a compare match with RTC compare channel 1.
1.4 Underflow Output Action
For each of the LETIMER outputs an underflow output action can be set. The configured output action is performed every time the counter underflows while the respective repeat register is nonzero. In PWM mode, the output is similarly only changed on COMP1 match if the repeat register is nonzero. The different output actions are shown in Table 2.2 (p. 5)
Table 2.2. LETIMER Underflow Output Actions
| UF0A0/UF0A1 | Mode | Description |
| 00 | Idle | The output is held at its idle value |
| 01 | Toggle | The output is toggled on LETIMERn_CNT underflow if LETIMERn_REPx is nonzero |
| 10 | Pulse | The output is held active for one clock cycle on LETIMERn_CNT underflow if LETIMERn_REPx is nonzero. It then returns to its idle value |
| 11 | PWM | The output is set idle on LETIMERn_CNT underflow and active on compare match with LETIMERn_COMP1 if LETIMERn_REPx is nonzero. |
The LETIMER outputs must be routed to pins using the LETIMERn_ROUTE register. The selected pins must be enabled as output in the GPIO module. Pin configuration is covered in AN0012 GPIO
1.5 Interrupts
There are 5 interrupts available in the LETIMER. One interrupt for when each of the Repeat Counters (REP0 and REP1) reaches zero, one when the LETIMER counter matches the value of each compare register (COMP0 and COMP1) and one when the LETIMER underflows.
These interrupts can be enabled, disabled and cleared using the following functions from the emlib:
• LETIMER_IntEnable(LETIMER_TypeDef *letimer, uint32_t flags) enables interrupts
• LETIMER_IntDisable(LETIMER_TypeDef *letimer, uint32_t flags) disables interrupts
• LETIMER_IntClear(LETIMER_TypeDef *letimer, uint32_t flags) clears interrupts
1.6 Register Access and Synchronization
Since the LETIMER is a Low Energy Peripheral and runs off a low frequency clock which is asynchronous to the HFCORECLK some register, writes need to be synchronized from the high frequency domain to the low frequency domain. The changes will not take effect until the synchronization is done and it takes 3 low frequency clock cycles to synchronize between the two domains.
After writing to a register that requires synchronization the correspondent flag in the LETIMERn_SYNCBUSY register will be set while the synchronization is in progress. Writing to the same register before the synchronization is complete may result in undefined behavior and therefore a wait cycle must be performed to ensure the register was synchronized. This can be done using the
LETIMER_Sync(LETIMER_TypeDef *letimer, uint32_t mask) function from the emlib. All emlib LETIMER functions check for synchronizations before writing the registers.
2 Configuration
The LETIMER can be easily and quickly configured using the LETIMER_Init(LETIMER_TypeDef *letimer, const LETIMER_Init_TypeDef *init) function from the emlib. This function allows the configuration of the following parameters:
• Start counting when the initialization is complete
• Counter running during debug
• Start counting on RTC COMP0 match
• Start counting on RTC COMP1 match
• Use COMP0 register as TOP value
• Load COMP1 to COMP0 when REP reaches 0
• Idle value for output 0
• Idle value for output 1
• Underflow output 0 action
• Underflow output 1 action
• Repeat mode
3 Software Examples
This application note contains two software examples demonstrating the LETIMER features. On project letimer_pwm_pulse the LETIMER runs in free mode and outputs a variable duty-cycle PWM signal on output 0 and pulses on output 1. On letimer_rtc_pulses project the LETIMER is triggered by the RTC and runs in One-shot mode with pulses output. The projects are intended for both the EFM32 Starter Kits (STK) and Development Kit (DK).
3.1 PWM and Pulses Output
On letimer_pwm_pulse project the LETIMER is configured to run in Free mode with PWM on output 1 (pin PD6, P5.9 on the DK protoboard) and pulses on output 0 (pin PD7, P5.10 on the DK protoboard). The value of COMP0 is used as TOP value for the counter and is loaded after each underflow. Using underflow interrupts the value of COMP1 is decremented throughout the program execution resulting in a variable PWM duty-cycle.
The PWM frequency and duty-cycle can be obtained using the formulas below.
| PWM Frequency Equation fPWM = 32768 / TOP | (4.1) |
| PWM Duty-cycle Equation DSPWM = COMP1 / COMP0 x 100 | (4.2) |
The purpose of this example is to demonstrate how the LETIMER can be used to output PWM and/or pulses with little CPU intervention and keeping the energy consumption to a minimum
3.2 RTC Triggered Counter
The letimer_rtc_pulses project demonstrates how the RTC can be used to trigger the LETIMER. The LETIMER is configured to start counting on RTC COMP0 match with pulses on output 0 (no action on output 1) and One-shot repeat mode. Figure 4.1 (p. 8) illustrates the program flow.
Figure 4.1. RTC Trigger
The RTC generates a compare match after 5 seconds (RTC_COMP0 = 5) of program execution which will trigger the LETIMER to start counting. The LETIMER will count-down while LETIMERn_REP0!=0 generating a pulse on each underflow. For this project LETIMER_REP0 has the value of 5 so there will be 5 pulses generated on pin PD6 (P5.9 on the DK protoboard).
| Note The RTC continues counting after the compare match. If it wraps around the top value and generates a new compare match the LETIMER will not be triggered because LETIMERn_REP0 = 0. |
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